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Verilog FPGA Recieve UART (Bit Identifier.v):
//////////////////////////////////////////////////////////////////
//
// This module takes the incoming data streem and searches for 6 out of 8
// entries to be either a 1 or a 0
//
//////////////////////////////////////////////////////////////////
// Copyright (C) Kenneth Y Maxon - 2003
//////////////////////////////////////////////////////////////////
module bit_identifier (
input wire clk,
input wire rst,
input wire stream_in,
output reg out_rx_one_75,
output reg out_rx_zero_75,
input wire sio_ce_x16
);
reg r1_sio_ce_x16,r2_sio_ce_x16;
reg [7:0] rx_input_shift_reg;
wire [1:0] sub_total1,sub_total2,sub_total3,sub_total4;
wire [2:0] mid_total1,mid_total2;
wire [3:0] total;
always @(posedge clk or posedge rst)
begin
if(rst)
begin
rx_input_shift_reg[7:0] <= #1 8'h00; // after reset start at 0 because the state machine must see a 1 to start
end
else if (sio_ce_x16)
begin
rx_input_shift_reg[7:0] <=
#1 {stream_in,rx_input_shift_reg[7:1]};
end
end
assign #1 sub_total1 = rx_input_shift_reg[0] + rx_input_shift_reg[1];
assign #1 sub_total2 = rx_input_shift_reg[2] + rx_input_shift_reg[3];
assign #1 sub_total3 = rx_input_shift_reg[4] + rx_input_shift_reg[5];
assign #1 sub_total4 = rx_input_shift_reg[6] + rx_input_shift_reg[7];
assign #1 mid_total1 = sub_total1 + sub_total2;
assign #1 mid_total2 = sub_total3 + sub_total4;
assign #1 total = mid_total1 + mid_total2;
assign #1 rx_one_75 = (total[3:0] >= 4'h6);
assign #1 rx_zero_75 = (total[3:0] <= 4'h2);
///////////////////////////////////////////////////////////////////
//
// The following inserts three 50MHz clocks worth of delay before
// assigning the output value of the ripple adder allowing it time
// to settle
//
// the first one delays a clock, the second one delays a clock
// and the third one makes the assignment after the time the second
// one asserts.
//
///////////////////////////////////////////////////////////////////
always @(posedge clk or posedge rst)
begin
if(rst)
begin
r1_sio_ce_x16 <= #1 1'b0;
end
else
begin
r1_sio_ce_x16 <= #1 sio_ce_x16;
end
end
always @(posedge clk or posedge rst)
begin
if(rst)
begin
r2_sio_ce_x16 <= #1 1'b0;
end
else
begin
r2_sio_ce_x16 <= #1 r1_sio_ce_x16;
end
end
always @(posedge clk or posedge rst)
begin
if(rst)
begin
out_rx_one_75 <= #1 1'b0;
out_rx_zero_75 <= #1 1'b0;
end
else if (r2_sio_ce_x16 == 1'b1) //delayed by 2 clocks to allow large combinatorial ripple to settle
begin
out_rx_one_75 <= #1 rx_one_75;
out_rx_zero_75 <= #1 rx_zero_75;
end
end
endmodule
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