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CRC332 Motherboard

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This is one of my more recent accomplishments. ('99-2000). This circuit card assembly is a MC68332 Data Sheet based platform designed specifically for small embedded robotics and motion control. This baby packs reasonable processing power as far as low end embedded processors go. For more details I suggest that you read the Seattle Robotics Society 'Encoder' article titled, 'Three processor platforms presented'. Back in the day I sold these embedded controller boards for awhile but gave it up after selling 62 in just a few short months. Too much work, and too little time to play with the robots!

Want to learn more? In addition to the rest of the information on this page, I have written a few articles for the Seattle Robotics Society's online magazine the Encoder. Click the read more link to the right which will take you to one such article.

Board level technologies used:

CRC332 Main board Schematics are provided below:

Schematic

Files Section

CRC_Boot_Code

Here is a bit of code to get you started. The link to the right will take you to the files section of my web page where you can download the software I developed while writing my first 68332 based article for the Seattle Robotics Society's Encoder Online Magazine. The code performs several function including what seems to be the most complex, initializing a chip select or two. Additionally, it drives a LCD, services 8 channels of AtoD, Outputs PWM based on the AtoD results, tracks an incremental encoder location as a 32bit integer and provides a great way to start learning system development with BDM32. For more information on this refer one of the many 68332 based robotics articles to the left.

I used to sell these commercially. I sold 62 in 2.5 months but then got burned out on all that soldering and assembly work. Anywho, there are just a few bare PCB's left that I'd be willing to sell for super cheap. If you want to make your own the artwork files are provided to the left, although those that I offer are silkscreened & solder masked. Anywho, check out the PCB, left.

Basic Motorola Manuals - 68332:

332_Tutorial(346K) 68332_Users_Manual(1,508K) CPU32_Manual(1,468K) SIMRM_Manual(1,169K) TPURM_Manual(769K) GPTRM_Manual(448K) QSMRM_Manual(1,299K)

CRC332 Prototype:

Click Image for Larger View

The image right shows the 2-layer prototype board I build to work out the bugs in the system. Since I designed this from the ground up and did several things not tried before like building my own BDM hardware into the ISPLSI1016E Data sheetCPLD, I decided it would be best to build a prototype version first before investing in production quality boards. The board to the left is just that. Click on it for a close up view, it's kind of cool to see that many traces on only two layers. The board itself was fabricated at AP-Circuits (there is a link at the bottom of the page) however the production versions that I sold were done by Advanced Circuits in Colorado (link also at the bottom of the page). The final versions had solder mask, solder paste and silk screening on both sides which was so crucial for assembly. In this prototype I put as much text on the copper layers as possible without shorting things out. Look close, it's there and while you are at it, just count all those through holes! Yup, there is a penny per hole fee and when you've only got two layers to play with, that adds up pretty quick. Advanced Circuits has no hole count limitations and I highly recommend their services.

This circuit card is highly noise emissive. It opens up the squelch on my 2-meter radio around 155MHz or anywhere close to the 7th or 5th harmonic of 22.1184MHz. The traces are in dire need of termination and a ground place for efficient energy return. Given that the traces terminate into an expansion connector, the last link in the point to point routing ends in a high-impedance. (yes, a true no-no in layout). Of course I didn't learn these rules until many years later. The routing is the easy part. Designing for immunity (RS) and lower emissions (RE) is were the art really lies. Back in the day when this work was completed, I naively believed the work was in the connectivity.


... BDM Stuff ...

BDM Startup Script:

mm 0xfffa01 ;b
0x4f
.
mm 0xfffa44 
0x3fae 
.
mm 0xfffa50 
0x1006
0x7870
.
mm 0xfffa21 ;b
0x00
.
mm 0xfffa1f ;b
0x00
.
rm pc 0x100000
rm ssp 0x108ffc
rm usp 0x107000
lo crc332.s19
md 0xfffa00 0x80
rd
dasm 0x100000 0x10

The following are two (non-Moto) BDM pods. These schematics are from A) a pod from Introl, and B) a pod by Gunder Magnuson. I've not personally used either of them but they are provided here for reference purposes. If you can afford it it's much easier to contact Mark C. (the maker of the MRM) and buy one of his BDM pods. While you are at it, pick up one of his MRM boards, it's well worth it.

BDM Schematic 1:

BDM Schematic 2:

I get lots of questions about how to start things off. the BDM code to the right is a good starting point of reference. This is the basic system chip configuration I used to test the CRC332 boards. It sets the basic registers and configures a few chip selects so that code can be loaded into RAM and executed.

BDM Software

The link to the left will take the reader to the files section of this web site where they can download a modified version of BD-32. This verison was modified by my friend Mark C. It allows for directly flash loading of S19 files across BDM.


... Assembly Stuff ...

I get lot's of questions about assembling these boards. Can you really do this stuff at home? The three photo's below show some of the very first attempts Mark, Jeff and I were able to accomplish in my kitchen with a standard toaster oven on three different designs. To learn more refer to the articles secton of this web site and read the article of oven soldering fine pitch surface mount parts.

Here's a quick look as to how it looks before it goes into the oven

Back in the day designs were not heavily provisioned heavily for debugging. With lower density packages it was easy enough to probe directly. In a few places, package adapters, such as the one pictured to the left from Emulation Technologies make debugging complex hardware interaction problems all the easier. In many later embedded processor designs, key interface signals are routed through debugging headers laid out for high density digital logic analyzer probing.

One of the wonders of this board is it's ability to interface to a large number of different end items through it's reconfigurable CPLDs. The code below can be used on the second CPLD to implement a generic Peripheral Interface Adapter (PIA) inciting much like an 8255.

PIA CPLD Code:

MODULE pia_cpld

TITLE 'this file describes the pld'

// DEFINE INPUTS
        GLB_ENB PIN 2;
        DATA8,DATA9,DATA10,DATA11 PIN 15,9,10,11;
        DATA12,DATA13,DATA14,DATA15 PIN 19,20,21,22;
        R_W PIN 25;
        ADDR0,ADDR1 PIN 26,27;
        L_CS7 PIN 28;
        TPUCH0 PIN 31;
// DEFINE OUTPUTS
        GLOBAL_ENABLE PIN 32 ISTYPE 'COM';
        PA0,PA1,PA2,PA3 PIN 37,38,39,40 ISTYPE 'COM';
        PA4,PA5,PA6,PA7 PIN 41,42,43,44 ISTYPE 'COM';
        PB0,PB1,PB2,PB3 PIN 3,4,5,6 ISTYPE 'COM';
        PB4,PB5,PB6,PB7 PIN 7,8,9,10 ISTYPE 'COM';
//DEFINE NODES
        REG0,REG1 NODE ISTYPE 'REG_D,BUFFER,KEEP';
        OUT1,OUT2,OUT3,OUT4 NODE ISTYPE 'REG_D,BUFFER,KEEP';
        OUT5,OUT6,OUT7,OUT8 NODE ISTYPE 'REG_D,BUFFER,KEEP';
        OUT9,OUT10,OUT11,OUT12 NODE ISTYPE 'REG_D,BUFFER,KEEP';
        OUT13,OUT14,OUT15,OUT16 NODE ISTYPE 'REG_D,BUFFER,KEEP';
//TEMPORARY NODES 'KEEP' NOT DEFINED SO THE COMPILER WILL REPLACE LATER
        TN1, TN2 NODE;
//DEFINE GROUPS
        DATA = [DATA15,DATA14,DATA13,DATA12,DATA11,DATA10,DATA9,DATA8];
        CONTROL_REGISTER = [REG1,REG0];
        OUT_REG1 = [OUT8,OUT7,OUT6,OUT5,OUT4,OUT3,OUT2,OUT1];
        OUT_REG2 = [OUT16,OUT15,OUT14,OUT13,OUT12,OUT11,OUT10,OUT9];
        PORTA = [PA7,PA6,PA5,PA4,PA3,PA2,PA1,PA0];
        PORTB = [PB7,PB6,PB5,PB4,PB3,PB2,PB1,PB0];
        ADDRESS = [ADDR1,ADDR0];
//DEFINE CONSTANTS THAT MAY BE USED
        H,L,X,Z,C,U = 1,0,.X.,.Z.,.C.,.U.;
//COMPILER DIRECTIVES
        PLSI PROPERTY 'ISP ON';
EQUATIONS
    CONTROL_REGISTER[1..0].D = DATA[1..0].PIN;
    CONTROL_REGISTER[1..0].CLK = [(!L_CS7 & (ADDRESS == [1,0]) & !R_W),
                                  (!L_CS7 & (ADDRESS == [1,0]) & !R_W)];
    OUT_REG1[7..0].D = DATA[7..0].PIN;
    TN1 = (!L_CS7 & (ADDRESS == [0,0]) & !R_W);
    OUT_REG1[7..0].CLK = [TN1,TN1,TN1,TN1,TN1,TN1,TN1,TN1];
    OUT_REG2[7..0].D = DATA[7..0].PIN;
    TN2 = (!L_CS7 & (ADDRESS == [0,1]) & !R_W);
    OUT_REG2[7..0].CLK = [TN2,TN2,TN2,TN2,TN2,TN2,TN2,TN2];
    PORTA[7..0] = OUT_REG1[7..0].Q;    PORTB[7..0] = OUT_REG2[7..0].Q;
    PORTA[7..0].OE = [REG0.Q,REG0.Q,REG0.Q,REG0.Q,
                      REG0.Q,REG0.Q,REG0.Q,REG0.Q];
    PORTB[7..0].OE = [REG1.Q,REG1.Q,REG1.Q,REG1.Q,
                      REG1.Q,REG1.Q,REG1.Q,REG1.Q];
    WHEN(ADDRESS == [0,0])THEN DATA[7..0] = PORTA.PIN;
    WHEN(ADDRESS == [0,1])THEN DATA[7..0] = PORTB.PIN;
    WHEN(ADDRESS == [1,0])THEN DATA[1..0] = CONTROL_REGISTER[1..0].Q;
//IN THE LINES BELOW IT IS IMPORTANT TO REFER TO THE SCHEMATIC AND
//NOTE THAT GLOBAL_ENABLE IS CONNECTED TO GLB_ENB.  THIS IS DONE
//FOR REASONS OF REDUCED OUTPUT ENABLES
    WHEN(!L_CS7 & R_W) THEN GLOBAL_ENABLE = 1;
    DATA[7..0].OE = [GLB_ENB,GLB_ENB,GLB_ENB,GLB_ENB,
                     GLB_ENB,GLB_ENB,GLB_ENB,GLB_ENB];
END

When configured as a PIA, the portion of the schematic for the second CPLD then looks like the following:

The two 8 bit ports (PA & PB) clearly visible in the schematic are re-programmable on a port (8-bit) by port basis w/respect to their configuration as an input or output.

Lattice 1016 CPLD PIA schematic

Lattice Web Site:

This system uses a CPLD for some of the glue logic. One option for CPLD configuration is to program them in-system, referred to as ISP (In-System Programming). The image to the left is of the Lattice Semiconductor ISP cable. It connects from the Parallel port of a standard desktop PC to some header pins designed into your target PCB. The PCB must be powered up in order to program the CPLD. Lattice (and others) provide the download program as part of their development software. Entry level versions of this software (synario or the newer Lever) can be downloaded from the Lattice web site, link to the right...

Primary CPLD Code that originally shipped with the CRC332:

MODULE ver2

TITLE 'versionnumber2'

// DEFINE INPUTS

DATA0 PIN 15;
DATA3 PIN 16;
DATA8 PIN 17;
DATA9 PIN 18;

R_W PIN 20;
L_CS2 PIN 22;
L_CS8 PIN 25;

YO_CLOCK PIN 11;
AUTOFEED PIN 5;
STROBE PIN 4;
SEL_INP PIN 7;
//RES PIN 3;
DSO PIN 9;

DSI PIN 40;

L_BERR PIN 28;
FREEZE PIN 30;
LOGIC_CLOCK PIN 35;
LOGIC_IO_1 PIN 37;
LOGIC_IO_2 PIN 38;
LOGIC_IO_3 PIN 39;
LOGIC_IO_4 PIN 42;
LOGIC_IO_5 PIN 43;
LOGIC_IO_6 PIN 44;
LOGIC_IO_7 PIN 3;
BIT8_BOOT PIN 10;

// DEFINE OUTPUTS

OUT_PAPER PIN 8 ISTYPE 'COM';
ERROR PIN 6 ISTYPE 'COM';
L_BKPT PIN 29 ISTYPE 'COM';
L_RESET PIN 19 ISTYPE 'COM';
W_R PIN 21 ISTYPE 'COM';
MCS2 PIN 26 ISTYPE 'COM';
DSACK0 PIN 27 ISTYPE 'COM';
V_LED PIN 41 ISTYPE 'COM';

//DEFINE NODES

S4,S3,S2,S1,S0	NODE ISTYPE 'REG_D,BUFFER,KEEP';

DA_NODE NODE ISTYPE 'REG_D,BUFFER,KEEP';

//DEFINE BIDIRECTIONALS

//DEFINE SPECIAL FUNCTION INPUTS

//DEFINE GENERICS AND DATA GROUPS
ONE =		[0,0,0,0,0];
TWO =		[0,0,0,0,1];
THREE =		[0,0,0,1,0];
FOUR =		[0,0,0,1,1];
FIVE =		[0,0,1,0,0];
SIX =		[0,0,1,0,1];
SEVEN =		[0,0,1,1,0];
EIGHT =		[0,0,1,1,1];
NINE =		[0,1,0,0,0];
TEN =		[0,1,0,0,1];
ELEVEN =	[0,1,0,1,0];
TWELVE =	[0,1,0,1,1];
THIRTEEN =	[0,1,1,0,0];
FOURTEEN =	[0,1,1,0,1];
FIFTEEN =	[0,1,1,1,0];
SIXTEEN =	[0,1,1,1,1];
SEVENTEEN =	[1,0,0,0,0];
EIGHTEEN =	[1,0,0,0,1];
NINETEEN =	[1,0,0,1,0];
TWENTY =	[1,0,0,1,1];
TWENTYONE =	[1,0,1,0,0];
TWENTYTWO =	[1,0,1,0,1];
TWENTYTHREE =	[1,0,1,1,0];
TWENTYFOUR =	[1,0,1,1,1];
TWENTYFIVE =	[1,1,0,0,0];
TWENTYSIX =	[1,1,0,0,1];
TWENTYSEVEN =	[1,1,0,1,0];
TWENTYEIGHT =	[1,1,0,1,1];
TWENTYNINE =	[1,1,1,0,0];
THIRTY =	[1,1,1,0,1];
THIRTYONE =	[1,1,1,1,0];
THIRTYTWO =	[1,1,1,1,1];

STATE_REG =	[S4,S3,S2,S1,S0];

H,L,X,Z,C,U = 1,0,.X.,.Z.,.C.,.U.;

PLSI PROPERTY 'ISP ON';
PLSI PROPERTY 'PULLUP ON';

EQUATIONS

//WHEN ((L_CS8 == 0) & (R_W == 1)) THEN LOGIC_IO_1 = DATA0.PIN;
//WHEN ((L_CS8 == 0) & (R_W == 1)) THEN LOGIC_IO_2 = DATA3.PIN;
//WHEN ((L_CS8 == 0) & (R_W == 1)) THEN LOGIC_IO_3 = DATA8.PIN;
//WHEN ((L_CS8 == 0) & (R_W == 1)) THEN LOGIC_IO_4 = DATA9.PIN;

//WHEN(R_W == 1) THEN DATA0.OE = 0;
//WHEN(R_W == 1) THEN DATA3.OE = 0;
//WHEN(R_W == 1) THEN DATA8.OE = 0;
//WHEN(R_W == 1) THEN DATA9.OE = 0;

//WHEN ((L_CS8 == 0) & (R_W == 0)) THEN DATA0 = LOGIC_IO_5;
//WHEN ((L_CS8 == 0) & (R_W == 0)) THEN DATA0.OE = 1;
//WHEN ((L_CS8 == 0) & (R_W == 0)) THEN DATA3 = LOGIC_IO_6;
//WHEN ((L_CS8 == 0) & (R_W == 0)) THEN DATA3.OE = 1;
//WHEN ((L_CS8 == 0) & (R_W == 0)) THEN DATA8 = LOGIC_IO_7;
//WHEN ((L_CS8 == 0) & (R_W == 0)) THEN DATA8.OE = 1;
//WHEN ((L_CS8 == 0) & (R_W == 0)) THEN DATA9 = BIT8_BOOT;
//WHEN ((L_CS8 == 0) & (R_W == 0)) THEN DATA9.OE = 1;

L_BERR = 1;
L_BERR.OE = 1;

L_BKPT = ((!DA_NODE.Q & L_RESET) & STROBE # LOGIC_IO_7);
L_BKPT.OE = 1;

DA_NODE.AR = !SEL_INP;
DA_NODE.D = 1;
DA_NODE.CLK = (!DSI # !AUTOFEED);


ERROR = FREEZE;
ERROR.OE = 1;

OUT_PAPER = !(DSO & FREEZE);
OUT_PAPER.OE = 1;

V_LED = FREEZE;
V_LED.OE = 1;

// RSET = !L_RESET;  THIS HAS TO BE FIXED AS THE WIRING OUTSIDE
// THE PART HAS CHANGED AND THE RES LINE IS NOW CONNECTED
// TO THE DSI LINE THROUGH A RESISTOR EXTERNAL TO THE PART.
// RSET.OE = 1;   SAME GOES FOR THIS LINE AS WELL.

W_R = !R_W;
W_R.OE = 1;

DATA0 = BIT8_BOOT;
DATA0.OE = (!L_RESET & R_W); //GOE = LOGIC_IO_2

DATA3 = 0;
DATA3.OE = (!L_RESET & R_W); //GOE = LOGIC_IO_2

DATA8 = 0;
DATA8.OE = (!L_RESET & R_W); //GOE = LOGIC_IO_2

DATA9 = 0;
DATA9.OE = (!L_RESET & R_W); //GOE = LOGIC_IO_2

MCS2.OE = 1;
DSACK0.OE = 1;

STATE_REG.CLK = [!YO_CLOCK,!YO_CLOCK,!YO_CLOCK,!YO_CLOCK,!YO_CLOCK];
STATE_DIAGRAM STATE_REG

STATE ONE:
	DSACK0 = 1;
	MCS2 = 0;
	IF (L_CS2 == 0) THEN TWO
	ELSE ONE

STATE TWO:
	DSACK0 = 1;
	MCS2 = 0;
	GOTO THREE;

STATE THREE:
	DSACK0 = 1;
	MCS2 = 0;
	GOTO FOUR;

STATE FOUR:
	DSACK0 = 1;
	MCS2 = 0;
	GOTO FIVE;

STATE FIVE:
	DSACK0 = 1;
	MCS2 = 0;
	GOTO SIX;

STATE SIX:
	DSACK0 = 1;
	MCS2 = 1;
	GOTO SEVEN;

STATE SEVEN:
	DSACK0 = 1;
	MCS2 = 1;
	GOTO EIGHT;

STATE EIGHT:
	DSACK0 = 1;
	MCS2 = 1;
	GOTO NINE;

STATE NINE:
	DSACK0 = 1;
	MCS2 = 1;
	GOTO TEN;

STATE TEN:
	DSACK0 = 1;
	MCS2 = 1;
	GOTO ELEVEN;

STATE ELEVEN:
	DSACK0 = 1;
	MCS2 = 1;
	GOTO TWELVE;

STATE TWELVE:
	DSACK0 = 1;
	MCS2 = 1;
	GOTO THIRTEEN;

STATE THIRTEEN:
	DSACK0 = 1;
	MCS2 = 1;
	GOTO FOURTEEN;

STATE FOURTEEN:
	DSACK0 = 1;
	MCS2 = 1;
	GOTO FIFTEEN;

STATE FIFTEEN:
	DSACK0 = 1;
	MCS2 = 1;
	GOTO SIXTEEN;

STATE SIXTEEN:
	DSACK0 = 1;
	MCS2 = 1;
	GOTO SEVENTEEN;

STATE SEVENTEEN:
	DSACK0 = 1;
	MCS2 = 1;
	GOTO EIGHTEEN;

STATE EIGHTEEN:
	DSACK0 = 1;
	MCS2 = 1;
	GOTO NINETEEN;

STATE NINETEEN:
	DSACK0 = 1;
	MCS2 = 1;
	GOTO TWENTY;

STATE TWENTY:
	DSACK0 = 1;
	MCS2 = 1;
	GOTO TWENTYONE;

STATE TWENTYONE:
	DSACK0 = 1;
	MCS2 = 1;
	GOTO TWENTYTWO;

STATE TWENTYTWO:
	DSACK0 = 1;
	MCS2 = 1;
	GOTO TWENTYTHREE;

STATE TWENTYTHREE:
	DSACK0 = 1;
	MCS2 = 1;
	GOTO TWENTYFOUR;

STATE TWENTYFOUR:
	DSACK0 = 1;
	MCS2 = 1;
	GOTO TWENTYFIVE;

STATE TWENTYFIVE:
	DSACK0 = 1;
	MCS2 = 1;
	GOTO TWENTYSIX;

STATE TWENTYSIX:
	DSACK0 = 1;
	MCS2 = 1;
	GOTO TWENTYSEVEN;

STATE TWENTYSEVEN:
	DSACK0 = 1;
	MCS2 = 1;
	GOTO TWENTYEIGHT;

STATE TWENTYEIGHT:
	DSACK0 = 1;
	MCS2 = 1;
	GOTO TWENTYNINE;

STATE TWENTYNINE:
	DSACK0 = 1;
	MCS2 = 0;
	GOTO THIRTY;

STATE THIRTY:
	DSACK0 = 1;
	MCS2 = 0;
	GOTO THIRTYONE;

STATE THIRTYONE:
	DSACK0 = 0;
	MCS2 = 0;
	GOTO THIRTYTWO;

STATE THIRTYTWO:
	DSACK0 = 0;
	MCS2 = 0;
	GOTO ONE;

END

I'd love to say that I just dreamed this up and poof, walla, there it is. The truth of the matter however is that this baord went through a prototyping phase before it becamed the fully populated finely tuned beast that it is today. The photo below shows an early prototype. You can see on of the bright yellow re-work wires on the lower right side of the picture.

... Early Prototype ...

The prototype

This tiny little PCB, (pictured, right), was used in conjunction with the header pins connected to the CPLD to facilitate connection of a spare crystal oscillator. In the image the outline of the oscillator, decoupling cap and series 22-ohm resistor have had their outlines darkened to delineate. On the far side of the header pins, the extra 5 signals are run to spare plated vias to simplify access.

And finally, the footprint for the finished board. Yep, there is a lot packed in there :)

For additional resource information, or help on trying to locate components, electrical or mechanical, refer to the Links section of this page, left.
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