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68332<=>FPGA development board:

68332<=>FPGA

Schematic:

One of the developments above lead me to spend some time (about one and one-half years later) investing in my own technology base and to jump in and get my feet wet in a FPGA based design.

The board hosts a MC68332-GCFC Data Sheet processor system with flash, RAM, CPLD, etc. All of these parts are 5v while the FPGA system is new enough (Spartan-IIE family Data Sheet) that it has 3.3v IO and a 1.8v core. This disjunct then dictates the implementation of level shifting circuitry (74ALVC164245 by Philips Semiconductor). There is a fourth power supply along the back edge of the board to provide higher voltage levels as input to an AC inverter module. The front edge of the board is populated completely with header pins and break out all the processor busses, as well as FPGA side busses and special outputs for interfacing to vision system prototypes and LCD displays.

The development code base for this project is fairly large. In a later (much later) section the reader will see that I used this board to interface to a number of LCDs driving prototype display panels. On top of holding the operating code and configuration code for the FPGA as well as fail safe duplicate backups for in-system programming with increased reliability, there is also a significant storage capacity requirement for graphics and fonts as well. This project was completed when monolithic flash memory was really starting to grow in capacity. The parts used in this design are AM29F032B parts that were originally produced by AMD before the memory division was split out to Spansion.

Board level technologies used:

There is a pretty good amount going on in the circuitry outlined below. I have provided the schematic to the right to help guide the reader through that circuitry. Please pay particular attention to the note on one of the pages that outlines the need for a few cuts and jumps. In the rush of the moment I failed to back annotate the needed cuts and jumps from the paper red-lined design into the captured schematic. As such there are ~16 signals on the noted page that will need to be hand checked / verified prior to use. The signals that require checking are the connections to the /OE and DIR pins on the 5v <=> 3v level shifters.

The CPLD provides bus drive ability while the processor is coming out of reset. The board also hosts a standard 10-pin BDM interface to load the processor, external flash and to step through code and debug memory / registers. I've used a number of BDM pods including the one I developed to run inside CPLD for the CRC332. In this project I'm using a pod from the MRM (MiniRoboMind) project, pictured right.

BDM Software

MRM Website:

The link to the left will take the reader to the files section of this web site where they can download a modified version of BD-32. This verison was modified by my friend Mark C. It allows for directly flash loading of S19 files across BDM. I've grabbed a screen shot, below...

The second link (right) is to the Mini-RoboMinds web site where, if the reader want's to play with some of this technology themselves, they can purchase a really great MRM 68332 based controller that will work with these tools.

So this work later went on to become a full color vision and display system. That work is pictured later on this site in Controllers-2, Section (54). If the reader looks closely, they can identify that all of the basic design features here flow from the CRC332 board design (section 00) and that the new technology here is built upon that foundation.

On the bottom of the board, roughtly underneath the FPGA is an Xilinx family flash-ROM. This flash-ROM device is inserted in the JTAG (IEEE-1149) chain with the FPGA. The two device progammers, pictured below, are used to download from a PC's serial port into the flash-ROM device. Since it is a RAM based device, upon boot, the FPGA serially shifts the information out of the flash to load it's configuration.

One of many adapters/interface boards used in this project. In the development of this project, there are many adapter boards and interface boards, used to level shift and interface the FPGA to a number of different devices. The interface board, shown right, is one such simple adapter. It provides level conversion and connectivity between the FPGA and RS232C levels. This conversion is done with a MAX3232 3.3v line driver w/integrated charge pump.

The two configuration cable devices below are both made by Xilinx. The one on the right is a parallel cable-3 that can be found for cheap on eBay these days. The one on the left is a Xilinx parallel cable-4 that is used with some of the more advanced FPGA features on their newer porducts like the Virtex family for simultaneously doing JTAG, Ethernet-PPP on JTAG, etc...

BDM SOFTWARE SCREEN-SHOT:

The next piece of code is the first Verilog code developed and run on this board. Often an exceedingly simple starting point is exactly that which is needed. In this case an oscilloscope was used to verify the output and proper board operation.

Through out these pages there exist numerous examples of complex Verilog implementations like the advanced color vision system and those boards used in the development of my robot named Dohn Joe, and others. It is somewhat fitting given the large size and complexity of those designs that this first test code is presented here, and the 2'nd simple instantiation of a block RAM, in the next example, below.

First Verilog Code run on board:

/*
  	an even simplererrrrer test because the other one has issues
*/

module even_top(proc_rw,proc_clock,proc_cs7,
		proc_data0,test_out0,test_out1,test_out2,
		data_bus_en,proc_ds);
	input proc_rw;
	input proc_clock;
	input proc_cs7;
	input proc_data0;
	output test_out0;
	output test_out1;
	output test_out2;
	output data_bus_en;
	input proc_ds;

reg test_out0;
reg test_out2;
wire test_out1;

always @(posedge proc_clock)
begin
	if((proc_cs7 == 0) && (proc_rw == 0) && (proc_ds == 0))
	{
		test_out0 <= #1 !test_out0;
		test_out2 <= #1 proc_data0;
	}
end

assign #1 test_out1 = proc_cs7;
assign data_bus_en = proc_cs7;

endmodule

Supporting User Constraints File (*.UCF):

NET "proc_clock" TNM_NET = "proc_clock";
TIMESPEC "TS_proc_clock" = PERIOD "proc_clock" 22 MHz HIGH 50 %;
#PACE: Start of Constraints extracted by PACE from the Design
NET "test_out2" LOC = "p71"  ;
NET "test_out2" IOSTANDARD = LVTTL;
NET "test_out1" LOC = "p70"  ;
NET "test_out1" IOSTANDARD = LVTTL;
NET "test_out0" LOC = "p69"  ;
NET "test_out0" IOSTANDARD = LVTTL;
NET "proc_rw" LOC = "p204"  ;
NET "proc_rw" IOSTANDARD = LVTTL;
NET "proc_ds" LOC = "p203"  ;
NET "proc_ds" IOSTANDARD = LVTTL;
NET "proc_data0" LOC = "p179"  ;
NET "proc_data0" IOSTANDARD = LVTTL;
NET "proc_cs7" LOC = "p109"  ;
NET "proc_cs7" IOSTANDARD = LVTTL;
NET "proc_clock" LOC = "p185"  ;
NET "proc_clock" IOSTANDARD = LVTTL;
NET "data_bus_en" LOC = "p112"  ;
NET "data_bus_en" IOSTANDARD = LVTTL;

This next code snippet is an absolutely invaluable tool for anyone beginning the integration of a processor loaded FPGA project. I also have a *.hex <=> *.h conversion tool used to generate the *.h file containing the raw data set to be loaded into the FPGA and included into the *.C build. Note, this is the file included in line #2, below. I will attempt to get this utility app posted to the files area in the coming days. The 2'nd code snippet below shows the output of the *.h file processed by the hex2h.exe application.

While reading the below code, refer back to the graphic schematic snippet, provided right. This snippet is a chunk from the completed schematic near the beginning of this page. Note that these five signals, after level translation (5v<=>3.3v) connect directly between port F pins on the processor and the FPGA via a 74ALS164245 IC. Note, the pull up resistors shown in this schematic are not necessary as the data lines are always driven by the afore mentioned level translation IC.

'332 FPGA load code snippet:

//include the file with the data here...
#include "fpgadata.h"
//update these two values with the include file base name...
#define BYTE_COUNT fpgadata_ByteCount
#define DATA(i)    fpgadata_Data[i]

//#define FPGA_SIMULATION   //for test purposes only

#define FPGA_PGM     0x0001  /*PP0*/
#define FPGA_INIT    0x0002  /*PP1*/
#define FPGA_CLK     0x0004  /*PP2*/
#define FPGA_DONE    0x0008  /*PP3*/
#define FPGA_DATA    0x0010  /*PP4*/

#define PADAT  cf_imm.pp.PADAT

int loadFpgaConfig(void)
{
    unsigned short data;
    unsigned short value;
    unsigned long i;
    int j;
    
    PADAT = 0;         //set /PGM low to start FPGA program sequence

    delay_usec(10);     //hold low for about 10 usecs
    
    value = FPGA_PGM;    //de-asserts /PGM to begin programming
    PADAT = value;
    feed_watchdog();
    
    //normally we'd check that /INIT is high before moving on...
    #ifndef FPGA_SIMULATION
        system_usec_timer = 0;
        while ((PADAT & FPGA_INIT) == 0)
        {
            if (system_usec_timer > 500)
            {
                feed_watchdog();
                dprintf("FPGA Config Error: timed out waiting for memory clear\n\r");
                return(1);
            }
        }
    #endif
    
    feed_watchdog();
    for(i=0;i>1;
        }
    }
    
    PADAT = FPGA_PGM; //leave /PGM de-asserted    
    feed_watchdog();
    
    //normally we'd wait for the DONE signal to go high before moving on...
    //also, if /INIT is low at this time, we have a programming error.
    #ifndef FPGA_SIMULATION
        system_usec_timer = 0;
        while ((PADAT & FPGA_DONE) == 0)
        {
            if ((PADAT & FPGA_INIT) == 0)
            {
                feed_watchdog();
                dprintf("FPGA Config Error: INIT indicates bad CRC\n\r");
                return (2);
            }
            if (system_usec_timer > 500)
            {
                feed_watchdog();
                dprintf("FPGA Config Error: timed out waiting for DONE to go high\n\r");
                return (3);
            }
        }
    #endif

    feed_watchdog();
    return(0);
}

Link to...

Files section 23:

The application executable, in the files section linked from the right, is designed to run native called from a command line on a PC. It requires a file titled fpgadata.hex and produces as its output a file titled fpgadata.h. To take advantage of this application the user should use the impact tool that ships with the Xilinx ISE tool set (web pack, foundation or other) and target that tool to create a PROM file in *.hex format with the name fpgadata.hex, or rename the file after it has been created. The input file must reside in the same directory as the application.

Hex2h.exe Output:

//header auto-generated by hex2h.exe

unsigned char fpgadata_Data[] = {
    0xff, 0xff, 0xff, 0xff, 0x55, 0x99, 0xaa, 0x66, 0x0c, 0x00, 0x01, 0x80, 0x00, 0x00, 0x00, 0xe0,
    0x0c, 0x80, 0x06, 0x80, 0x00, 0x00, 0x00, 0xd0, 0x0c, 0x80, 0x04, 0x80, 0x00, 0x01, 0xfc, 0xb4,
    0x0c, 0x00, 0x03, 0x80, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x01, 0x80, 0x00, 0x00, 0x00, 0x90,
		.
		.
		.
		.
    0x00, 0x00, 0x87, 0x5a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
    0x00, 0x00, 0x00, 0x00    };

unsigned long fpgadata_ByteCount = 78756;

Board level CPLD support code:

MODULE e_332_pld

TITLE 'engineering board 332 part'

DATA0 PIN 16 ISTYPE 'COM';
DATA3 PIN 15 ISTYPE 'COM';
DATA8 PIN 19 ISTYPE 'COM';
DATA9 PIN 20 ISTYPE 'COM';
DATA10 PIN 21 ISTYPE 'COM';
DATA11 PIN 22 ISTYPE 'COM';
DATA12 PIN 23 ISTYPE 'COM';
DATA13 PIN 24 ISTYPE 'COM';
DATA14 PIN 25 ISTYPE 'COM';
DATA15 PIN 26 ISTYPE 'COM';

R_W PIN 9 ISTYPE 'COM';
W_R PIN 10 ISTYPE 'COM';
//L_DS PIN 11 ISTYPE 'COM';
FREEZE PIN 12 ISTYPE 'COM';
L_RESET PIN 14 ISTYPE 'COM';
V_LED PIN 36 ISTYPE 'COM';

EQUATIONS

W_R = !R_W;
W_R.OE = 1;

V_LED = (FREEZE # !L_RESET);
V_LED.OE = 1;

DATA0 = 0;
DATA0.OE = (!L_RESET & R_W);
DATA3 = 0;
DATA3.OE = (!L_RESET & R_W);
DATA8 = 0;
DATA8.OE = (!L_RESET & R_W);
DATA9 = 0;
DATA9.OE = (!L_RESET & R_W);
DATA10 = 1;
DATA10.OE = (!L_RESET & R_W);
DATA11 = 1;
DATA11.OE = (!L_RESET & R_W);
DATA12 = 1;
DATA12.OE = (!L_RESET & R_W);
DATA13 = 1;
DATA13.OE = (!L_RESET & R_W);
DATA14 = 1;
DATA14.OE = (!L_RESET & R_W);
DATA15 = 1;
DATA15.OE = (!L_RESET & R_W);

END

This project was not only about developing FPGA based technologies for the fun of it. Sure there was a massive learning curve that I've undertaken and I'll now be able to apply this technology to other projects, however the immediate goal for this work was to develop LCD controller. The image below shows the Sharp LCD (LQ049B4DG01) that I was developing with mounted to the board. Some of these displays are designed for the automotive industry which means that they have incredible contrast performance in the high end brightness category.

For additional resource information, or help on trying to locate components, electrical or mechanical, refer to the Links section of this page, left.
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