In designing a system such as this getting access to all of the signals for verification and tracking down of that one last timing issue becomes critical. Shown left is a smile tracking display fixture I used on my digital logic analyzer to troubleshoot the last clocking problem. It turns out that this problem was an artifact of settling times due to a difference of 2.5ns routing delay on one of the signals in my CPLD which caused one signal to become active slightly before the data acted on by that signal. To the left the reader can see an image of the test fixture interface to the board. At this point it becomes painfully obvious why one would take the time to build a large prototype board with all of the system interfaces and break out points on it before finally committing to a small compact board for the final unit.
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