This project has involved the development of a specialized TFT display driver. There are two main blocks that working together complete this design. First is the Motorola 68332 processor system. The use of a traditional style processor with bus cycles that can be externally terminated is of paramount importance here. This provides for interaction between the processor system and the second major block of the design which is the complex state machine running with-in the CPLD on the board. This CPLD uses 1-Meg/byte of 10-ns Static RAM as a pseudo-dual port. I refer to it as pseudo-dual port as it is really, just common static RAM with the exception of being really fast. The critical detail here is that the state machine arbitrates and controls data flow between the processor systems address and data busses and the RAM buffer as well as fetching data from the same buffers and piping it to the display screen.
Click Image To Return:
