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Verilog FPGA SPI Instantiation:
parameter SPI_REG_ADDR = 12'h004;
parameter FPGA_RST_ADDR = 16'h0009;
reg [1:0] qual_counter;
wire qual_data;
wire [7:0] spi_data_out;
wire spi_irq_o;
wire ack_4;
wire proc_irq;
always @(posedge sys_clock)
begin
if(proc_cs)
qual_counter[1:0] <= #1 2'b00;
else
qual_counter[1:0] <= qual_counter[1:0] + 2'b01;
end
assign #1 qual_data = ((qual_counter[1:0] == 2'b01) && (~proc_rw));
assign #1 proc_data[7:0] = (~proc_cs && proc_rw && (proc_addr[15:4] == SPI_REG_ADDR)) ?
spi_data_out[7:0] : 8'bzzzzzzzz;
assign #1 proc_data[7:0] = (~proc_cs && proc_rw && (proc_addr[15:0] == IRQ_REG_ADDR)) ?
{1'b0,1'b0,1'b0,1'b0,spi_irq_o,i2c1_irq_o,i2c2_irq_o,i2c3_irq_o} :
8'bzzzzzzzz;
assign #1 proc_irq = spi_irq_o | i2c1_irq_o | i2c2_irq_o | i2c3_irq_o;
simple_spi_top my_spi(
.clk_i(sys_clock),
.rst_i(~((proc_addr[15:0] == FPGA_RST_ADDR) && (qual_data))),
.cyc_i(((qual_counter[1:0] == 2'h2) || (qual_counter[1:0] == 2'h3)) &&
(proc_addr[15:4] == SPI_REG_ADDR)),
.stb_i(((qual_counter[1:0] == 2'h2) || (qual_counter[1:0] == 2'h3)) &&
(proc_addr[15:4] == SPI_REG_ADDR)),
.adr_i(proc_addr[1:0]),
.we_i(~proc_rw),
.dat_i(proc_data[7:0]),
.dat_o(spi_data_out[7:0]),
.ack_o(ack_4),
.inta_o(spi_irq_o),
.sck_o(spi_sck),
.mosi_o(spi_mosi),
.miso_i(spi_miso)
);
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