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Verilog instantiation template-24'bit encoder:
// encoder_1a & encoder_1b are inputs for the 2 channels of the physical device // after buffering and 5v => 3.3v converstion. parameter ENCODER1_ADDR = 12'h006; parameter FPGA_RST_ADDR = 16'h0009; wire [7:0] encoder1_data_out; reg [1:0] qual_counter; wire qual_data; always @(posedge sys_clock) begin if(proc_cs) qual_counter[1:0] <= #1 2'b00; else qual_counter[1:0] <= qual_counter[1:0] + 2'b01; end assign #1 qual_data = ((qual_counter[1:0] == 2'b01) && (~proc_rw)); assign #1 proc_data[7:0] = (~proc_cs && proc_rw && (proc_addr[15:4] == ENCODER1_ADDR)) ? encoder1_data_out[7:0] : 8'bzzzzzzzz; encoder_func enc1( .sys_clock(sys_clock), .encoder_data_out(encoder1_data_out[7:0]), .proc_addr(proc_addr[1:0]), .strobe(qual_data && (proc_addr[15:4] == ENCODER1_ADDR)), .reset(qual_data && (proc_addr[15:0] == FPGA_RST_ADDR)), .encoder_a(encoder_1a), .encoder_b(encoder_1b) ); |