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Verilog Instantiation template:


parameter PWM_ADDR1 = 16'h0005;
parameter FPGA_RST_ADDR = 16'h0009;

reg [1:0] qual_counter;
reg qual_data;

always @(posedge sys_clock)
begin
	if(proc_cs)
		qual_counter[1:0] <= #1 2'b00;
	else
		qual_counter[1:0] <= qual_counter[1:0] + 2'b01;
end

assign #1 qual_data = ((qual_counter[1:0] == 2'b01) && (~proc_rw));

locked_antiphase my_anti(
	.sys_clock(sys_clock),
	.proc_data(proc_data[7:0]),
	.strobe(qual_data && (proc_addr[15:0] == PWM_ADDR1)),
	.reset(qual_data && (proc_addr[15:0] == FPGA_RST_ADDR)),
	.antiphase_pwm(motor1_dir)
	);

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