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Verilog PWM Code:
//==========================================================
//
// Module for driving 8 bit locked antiphase
//
// By: Kenneth Maxon 12/03/04
//
//==========================================================
module locked_antiphase(
input wire sys_clock,
input wire [7:0] proc_data,
input wire strobe,
input wire reset,
output wire antiphase_pwm
);
parameter CLOCK_OVERFLOW = 9'd555;
//--------------------------- local registers
reg [8:0] clock_count;
reg [7:0] pwm_reg;
reg [7:0] pwm_count;
wire pwm_tick;
//--------------------------- clock divider
always @(posedge sys_clock or posedge reset)
begin
if(reset)
clock_count <= #1 9'h000;
else
begin
if(clock_count <= CLOCK_OVERFLOW)
clock_count[8:0] <= #1 clock_count + 9'h001;
else
clock_count[8:0] <= #1 9'h000;
end
end
// in the following line pwm_tick is asserted once every 555 clocks
// this gives about 90KHz from a 50MHz oscillator
assign #1 pwm_tick = clock_count[8:0] == CLOCK_OVERFLOW;
//--------------------------- data bus register latch
always @(posedge sys_clock or posedge reset)
begin
if(reset)
pwm_reg[7:0] <= #1 8'h80;
else if (strobe)
pwm_reg[7:0] <= #1 proc_data[7:0];
end
//--------------------------- pwm function
always @(posedge sys_clock or posedge reset)
begin
if(reset)
pwm_count[7:0] <= #1 8'h0;
else if(pwm_tick)
pwm_count[7:0] <= #1 pwm_count[7:0] + 8'h01;
end
assign #1 antiphase_pwm = pwm_count[7:0] < pwm_reg;
endmodule
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