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Verilog FPGA Recieve UART (TOP):
//////////////////////////////////////////////////////////////////
//
// rx_uart Module -KYM
//
// This is the UART section for recieve only.
//
//////////////////////////////////////////////////////////////////
// Copyright (C) Kenneth Y Maxon - 2003
//////////////////////////////////////////////////////////////////
module rx_uart(
input wire clk,
input wire rst,
input wire rxd_i,
input wire sio_ce_x16,
output wire [7:0] dout_o,
input wire re_i,
output wire empty_o
);
`include "timescale.v"
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
///////////////////////////////////////////////////////////////////
reg [4:0] bit_width_counter;
wire [6:0] rx_mem_state;
reg [8:0] data_collection_sr;
reg [3:0] bits_recieved_count;
wire clear_bits_recieved_count_command;
wire bit_width_counter_clear;
wire sample_data_command;
wire move_data_to_fifo_command;
wire out_rx_one_75,out_rx_zero_75;
///////////////////////////////////////////////////////////////////
//
// IO Fifo's
//
///////////////////////////////////////////////////////////////////
fifo_33 #(8) rx_fifo(
.clk(clk),
.rst(rst),
.din(data_collection_sr[7:0]),
.we(move_data_to_fifo_command),
.dout(dout_o),
.re(re_i),
.full(recieve_fifo_full),
.empty(empty_o)
);
///////////////////////////////////////////////////////////////////
//
// Bit Identifier (8x)
//
///////////////////////////////////////////////////////////////////
bit_identifier my_bit_identifier(
.clk(clk),
.rst(rst),
.stream_in(rxd_i),
.out_rx_one_75(out_rx_one_75),
.out_rx_zero_75(out_rx_zero_75),
.sio_ce_x16(sio_ce_x16)
);
///////////////////////////////////////////////////////////////////
//
// bit shift register (uart recieve pipe) & bits recieved counter
//
///////////////////////////////////////////////////////////////////
always @(posedge clk)
begin
if(rst | clear_bits_recieved_count_command)
begin
data_collection_sr[8:0] <= #1 9'h000;
bits_recieved_count[3:0] <= #1 4'h0;
end
else if(sample_data_command)
begin
data_collection_sr[8:0] <= #1 {rxd_i,data_collection_sr[8:1]};
bits_recieved_count[3:0] <= #1 bits_recieved_count[3:0] + 4'h1;
end
end
//
// bit width counter. This counter is cleared by a successful mid bit detection
// of the start bit. It is also cleared after each successive sample.
//
always @(posedge clk)
begin
if(rst | bit_width_counter_clear)
begin
bit_width_counter[4:0] <= #1 5'h00;
end
else if(sio_ce_x16)
begin
bit_width_counter[4:0] <= #1 bit_width_counter[4:0] + 5'h01;
end
end
///////////////////////////////////////////////////////////////////
//
// Recieve state machine
//
///////////////////////////////////////////////////////////////////
rx_uart_fsm my_rx_uart_fsm(
.rst(rst),
.clk(clk),
.rx_mem_state(rx_mem_state[6:0]),
.out_rx_one_75(out_rx_one_75),
.out_rx_zero_75(out_rx_zero_75),
.bit_width_counter(bit_width_counter[4:0]),
.bits_recieved_count(bits_recieved_count[3:0]),
.data_collection_sr_last_bit(data_collection_sr[8]),
.recieve_fifo_full(recieve_fifo_full)
);
rx_uart_assn my_rx_uart_assn(
.rx_mem_state(rx_mem_state[6:0]),
.clear_bits_recieved_count_command(clear_bits_recieved_count_command),
.bit_width_counter_clear(bit_width_counter_clear),
.sample_data_command(sample_data_command),
.move_data_to_fifo_command(move_data_to_fifo_command)
);
endmodule
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