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Verilog FPGA Recieve UART (RXE_Uart_assn.v):


//////////////////////////////////////////////////////////////////
//
//  rx_uart_FSM_assigner module
//
//////////////////////////////////////////////////////////////////
//  Copyright (C) Kenneth Y Maxon - 2003
//////////////////////////////////////////////////////////////////

module rxe_uart_assn(
			input wire [8:0] rx_mem_state,
			output reg clear_bits_recieved_count_command,
			output reg bit_width_counter_clear,
			output reg sample_data_command,
			output reg move_data_to_fifo_command,
			output reg test_out
			);

`include "timescale.v"

parameter[8:0]
	RX_1_CASE		= 9'bxxxxxxxx1,	// 01
	RX_2_CASE		= 9'bxxxxxxx1x,	// 02
	RX_21_CASE		= 9'bxxxxxx1xx,	// 02
	RX_22_CASE		= 9'bxxxxx1xxx,	// 02
	RX_3_CASE		= 9'bxxxx1xxxx,	// 04
	RX_4_CASE		= 9'bxxx1xxxxx,	// 08
	RX_5_CASE		= 9'bxx1xxxxxx,	// 10
	RX_6_CASE		= 9'bx1xxxxxxx,	// 20
	RX_7_CASE		= 9'b1xxxxxxxx;	// 40

always @(rx_mem_state)
begin 
	casex (rx_mem_state) // synopsys parallel_case full_case

		RX_1_CASE:  //0001
		begin
			clear_bits_recieved_count_command = 1'b1;
			bit_width_counter_clear = 1'b1;  // keep the counter in reset
			sample_data_command = 1'b0;
			move_data_to_fifo_command = 1'b0;
			test_out = 1'b0;
		end
		RX_2_CASE:  //0002
		begin
			clear_bits_recieved_count_command = 1'b1;
			bit_width_counter_clear = 1'b1;  // keep the counter in reset
			sample_data_command = 1'b0;
			move_data_to_fifo_command = 1'b0;
			test_out = 1'b0;
		end
		RX_21_CASE:  //0002
		begin
			clear_bits_recieved_count_command = 1'b1;
			bit_width_counter_clear = 1'b0;  // keep the counter in reset
			sample_data_command = 1'b0;
			move_data_to_fifo_command = 1'b0;
			test_out = 1'b0;
		end
		RX_22_CASE:  //0002
		begin
			clear_bits_recieved_count_command = 1'b1;
			bit_width_counter_clear = 1'b1;  // keep the counter in reset
			sample_data_command = 1'b0;
			move_data_to_fifo_command = 1'b0;
			test_out = 1'b0;
		end
		RX_3_CASE:  //0003
		begin
			clear_bits_recieved_count_command = 1'b0;
			bit_width_counter_clear = 1'b0;
			sample_data_command = 1'b0;
			move_data_to_fifo_command = 1'b0;
			test_out = 1'b0;
		end
		RX_4_CASE:  //0004
		begin
			clear_bits_recieved_count_command = 1'b0;
			bit_width_counter_clear = 1'b1;	// reset the bit width counter so we sample in the middle of the next bit
			sample_data_command = 1'b1;  // oh yeah, take a sample too.
			move_data_to_fifo_command = 1'b0;
			test_out = 1'b1;
		end
		RX_5_CASE:  //0005
		begin
			clear_bits_recieved_count_command = 1'b0;
			bit_width_counter_clear = 1'b0;
			sample_data_command = 1'b0;
			move_data_to_fifo_command = 1'b0;
			test_out = 1'b0;
		end
		RX_6_CASE:  //0006
		begin
			clear_bits_recieved_count_command = 1'b0;
			bit_width_counter_clear = 1'b0;
			sample_data_command = 1'b0;
			move_data_to_fifo_command = 1'b0;
			test_out = 1'b0;
		end
		RX_7_CASE:  //0007
		begin
			clear_bits_recieved_count_command = 1'b0;
			bit_width_counter_clear = 1'b0;
			sample_data_command = 1'b0;
			move_data_to_fifo_command = 1'b1;	// and now save the data into the uart
			test_out = 1'b0;
		end
	endcase
end // rx_machine

endmodule

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