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Verilog FPGA Recieve UART (rxe_uart_fsm.v):


///////////////////////////////////////////////////////////////////////
//   
//  Module rx_machine
//
//			This module is the FSM for the mdsb_recieve side
//
///////////////////////////////////////////////////////////////////////
//  Copyright (C) Kenneth Y Maxon - 2003
//////////////////////////////////////////////////////////////////

module rxe_uart_fsm(
			input wire rst,
			input wire clk,
			output reg [8:0] rx_mem_state,
			input wire out_rx_one_75,
			input wire out_rx_zero_75,
			input wire [4:0] bit_width_counter,
			input wire [3:0] bits_recieved_count,
			input wire data_collection_sr_last_bit,
			input wire recieve_fifo_full
			);

parameter[8:0]
	RX_1_STATE		= 9'b000000001,	// 01
	RX_2_STATE		= 9'b000000010,	// 02
	RX_21_STATE		= 9'b000000100,	// 02
	RX_22_STATE		= 9'b000001000,	// 02
	RX_3_STATE		= 9'b000010000,	// 04
	RX_4_STATE		= 9'b000100000,	// 08
	RX_5_STATE		= 9'b001000000,	// 10
	RX_6_STATE		= 9'b010000000,	// 20
	RX_7_STATE		= 9'b100000000;	// 40

parameter[8:0]
	RX_1_CASE		= 9'bxxxxxxxx1,	// 01
	RX_2_CASE		= 9'bxxxxxxx1x,	// 02
	RX_21_CASE		= 9'bxxxxxx1xx,	// 02
	RX_22_CASE		= 9'bxxxxx1xxx,	// 02
	RX_3_CASE		= 9'bxxxx1xxxx,	// 04
	RX_4_CASE		= 9'bxxx1xxxxx,	// 08
	RX_5_CASE		= 9'bxx1xxxxxx,	// 10
	RX_6_CASE		= 9'bx1xxxxxxx,	// 20
	RX_7_CASE		= 9'b1xxxxxxxx;	// 40

always @(posedge clk or posedge rst) begin
	if (rst)
	begin
		rx_mem_state <= #1 RX_1_STATE;
	end
	else begin
		casex (rx_mem_state) // synopsys parallel_case full_case

		RX_1_CASE:  //0001
		begin
			if(!out_rx_one_75)
				rx_mem_state <= #1 RX_1_STATE;
			else
				rx_mem_state <= #1 RX_2_STATE;
		end

		RX_2_CASE:  //0002
		begin
			if(!out_rx_zero_75)
				rx_mem_state <= #1 RX_2_STATE;
			else
				rx_mem_state <= #1 RX_21_STATE;
		end

		RX_21_CASE:  //0003
		begin
			if(bit_width_counter[4:0] != 5'h05)
				rx_mem_state <= #1 RX_21_STATE;	// add a delay
			else
				rx_mem_state <= #1 RX_22_STATE;
		end

		RX_22_CASE:  //0003
		begin
			rx_mem_state <= #1 RX_3_STATE;	// clear the bit width counter
		end

		RX_3_CASE:  //0003
		begin
//			if(bit_width_counter[4:0] != 5'h10)
//			this was 16 (10H) I changed it to add 5 more counts so
//			that we'd start later into the bit so that we can
//			creep forward as we progress further into the byte
//			due to the baud rate miss-alignment.

			if(bit_width_counter[4:0] != 5'h10)
				rx_mem_state <= #1 RX_3_STATE;	// wait for a 16 count
			else
				rx_mem_state <= #1 RX_4_STATE;
		end

		RX_4_CASE:  //0004
		begin		// we'll sample here and also reset the bit width counter
			rx_mem_state <= #1 RX_5_STATE;  // also increment the bits recieved counter
		end

		RX_5_CASE:  //0005
		begin
			if(bits_recieved_count[3:0] != 4'h9)
				rx_mem_state <= #1 RX_3_STATE;	// loop if all bits not recieved
			else
				rx_mem_state <= #1 RX_6_STATE;
		end

		RX_6_CASE:  //0006
		begin
			if((data_collection_sr_last_bit == 1) && (!recieve_fifo_full))
				rx_mem_state <= #1 RX_7_STATE;	// valid start bit and fifo not full???
			else
				rx_mem_state <= #1 RX_1_STATE;	// invalid start bit or fifo full restart everything.
		end

		RX_7_CASE:  //0007
		begin
			rx_mem_state <= #1 RX_1_STATE;	// save the byte to the fifo.
		end

		endcase
	end
end

endmodule

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